Project Overview
PCB Layers
4
Signal / GND / PWR / Signal
Form Factor
~57mm
× 26mm compact module
Components
26
Unique references
DRC Errors
0
0 violations
This is a custom development board built around the ESP32-S3-MINI-1-N8 — Espressif's compact Wi-Fi and Bluetooth 5.0 module. The goal was to design something equivalent to a commercial dev board entirely from scratch: full control over every component, every trace, and every design decision. It breaks out all usable GPIOs, adds an on-board temperature and humidity sensor, an addressable RGB LED, and powers from a single USB-C cable or 5V rail.
The entire design was done in KiCad 9, from schematic capture through to manufacturing-ready Gerber files, targeting JLCPCB's 4-layer process with the JLC04161H-3313 stackup. The USB differential pair was analysed for impedance using IPC-2141 calculations matched to that specific stackup, and all design rules were verified clean before ordering.
This was completed as an independent project during second year Electrical and Electronics Engineering at the University of Western Australia.
⚠ Note: The 3V3 header pin is a regulated output only — do not apply external voltage to it. The TLV75801 LDO has no back-drive protection; powering through 3V3 with USB disconnected will damage the IC. Power the board via USB-C only. See Rev 2 for a planned fix.
Interactive 3D viewer — drag to rotate, scroll to zoom
PCB — top-down render
GPIO Pinout Reference
A complete pinout reference for both headers is available below. Every pin is listed with its GPIO number and all alternate functions — ADC, touch, RTC, UART, SPI, JTAG, and I²C — verified against the ESP32-S3-MINI-1 Datasheet v1.2. Strapping pins (GPIO45, GPIO46) are clearly flagged since they affect boot behaviour and should be treated with care in your own designs.
Full interactive pinout reference with color-coded function tags and connector lines to each pin pad.
📌 Open Full Pinout Reference →Left Header (J2) — 22 pins
3V3, GNDPower rails
GPIO1–10ADC1 + Touch + RTC
GPIO11–14ADC2 + Touch + RTC
GPIO15–16ADC2 + RTC + 32kHz
GPIO17 (SCL)I²C — ENS210
GPIO18 (SDA)I²C — ENS210
GND, 5VGround + USB VBUS
Right Header (J3) — 22 pins
3V3, GNDPower rails
GPIO45, GPIO46⚠ Strapping pins
GPIO43 (TX), GPIO44 (RX)UART0
GPIO39–42JTAG TCK/TDO/TDI/TMS
GPIO33–38FSPI / SPI2
GPIO48On-board RGB LED
GND, 5VGround + USB VBUS
Bill of Materials
| Reference | Part Number | Description | Qty | Notes |
|---|---|---|---|---|
| Microcontroller | ||||
| U4 | ESP32-S3-MINI-1-N8 | Main MCU — Wi-Fi / BT5.0 / 8MB Flash | 1 | GPIO19/20 USB D±, not broken out to headers. |
| Power | ||||
| U2 | TLV75801PDRVR | 800mA LDO Regulator — 5V → 3.3V | 1 | WSON-6. RθJA = 80.3°C/W. Thermal pad to GND. |
| R3, R4 | 1MΩ / 200kΩ | LDO Output Voltage Setting | 2 | Feedback divider — sets TLV75801 output to 3.3V. |
| USB & Protection | ||||
| J1 | USB4105-GF-A | USB-C Receptacle — 16P Top Mount | 1 | CC1/CC2 pulled to GND via 5.1kΩ — signals USB device mode to host. |
| U1 | D3V3XA4B10LP | 4-line USB TVS ESD protection | 1 | UDFN-10. Protects VBUS, D+, D−. |
| R1, R2 | RC0603FR-075K1L | 5.1kΩ USB-C CC Resistors | 2 | Signals UFP (device) mode to USB host. |
| Sensors & Indicators | ||||
| U3 | ENS210-LQFM | Temperature & Humidity Sensor — I²C | 1 | QFN-4. SCL→GPIO17, SDA→GPIO18. |
| D1 | WS2812B | Addressable RGB LED — PLCC4 | 1 | GPIO48 data line. 3.3V powered — below WS2812B min. VDD (3.5V), see Rev 2. |
| D2 | 150060RS75000 | Red Status LED — 0603 | 1 | Power-on indicator. Current limited by R5. |
| R5 | RC0603FR-07680RL | 680Ω LED Current Limiter | 1 | Series resistor for D2 status LED — ~1.9mA at 3.3V. |
| Passives | ||||
| C2, C4, C5, C6 | CC0603KRX7R7BB104 | 100nF Decoupling Capacitor — 0603 | 4 | Placed adjacent to each IC power pin. |
| C1, C3, C7 | CL10A106MQ8NNNC | 10µF Bulk Capacitor — 0603 | 3 | LDO input, LDO output, and 3V3 rail. |
| R6, R7, R8 | RC0603FR-0710KL | 10kΩ Pull-up Resistors | 3 | EN (R7), I²C SCL (R6), I²C SDA (R8). |
| Connectors & Buttons | ||||
| J2, J3 | 61302211121 | 1×22 Pin Header — 2.54mm vertical | 2 | Full GPIO breakout, 2.54mm pitch. |
| BOOT1, RESET1 | PTS810 SJG 250 | SMD Tactile Button — SPST | 2 | BOOT→GPIO0, RESET→EN. |
Design Specifications
PCB Stack-up — JLCPCB JLC04161H-3313
Total board thickness1.6 mm ±10%
Outer copper (L1/L4)1 oz (35µm)
PP prepreg type3313×1
PP prepreg thickness (L1→L2)0.0994 mm
Dielectric constant (Dk)4.4 (prepreg)
Core thickness1.265 mm
Inner copper (L2/L3)0.5 oz (15.2µm)
KiCad Design Rules — JLCPCB
Min copper clearance0.15 mm
Default track width0.20 mm
Via size / drill0.60 mm / 0.3 mm
Min via diameter0.45 mm (DRC minimum)
DP width (USB D±)0.15 mm
DP gap (USB D±)0.15 mm
Hole to hole clearance0.5 mm
Copper to edge0.3 mm
USB Differential Pair — IPC-2141 (Recalculated for JLCPCB)
Target impedance (Zd)90 Ω ±15%
Trace typeEdge Coupled Microstrip
PP prepreg height (h)0.0994 mm (3313)
Dielectric constant (Dk)4.4
Trace spacing (s)0.15 mm (6 mil)
IPC-2141 target width (w)0.142 mm (5.59 mil) → 90 Ω
Actual routed width0.15 mm — slightly wider → ~88 Ω
USB operating speedFull Speed (12 Mbps)
Power Architecture
Input5V via USB-C VBUS
Regulated output3.3V / 800mA max
LDO packageWSON-6 (thermal pad)
RθJA80.3°C/W
Power diss. @ 300mA0.51W → +41°C rise
ESD protectionD3V3XA4B10LP TVS on USB
Design Process
Phase 1 — Schematic Capture
Component selection and schematic design in KiCad 9
Selected components referencing Espressif application notes and IC datasheets. Designed full schematic including USB-C with CC pull-downs, TLV75801 LDO, ENS210 I²C sensor, WS2812B RGB LED, and GPIO breakout. ERC verified with 0 errors.
Full schematic — KiCad 9 schematic editor
Phase 2 — Impedance, Constraints & Netclasses
IPC-2141 differential pair impedance for JLCPCB JLC04161H-3313 stackup
Used JLCPCB stackup JLC04161H-3313: PP prepreg 3313×1 with h = 0.0994 mm and Dk = 4.4. Applied IPC-2141 edge-coupled microstrip formula — the calculated target trace width for exactly 90 Ω differential is 0.142 mm (5.59 mil) at 0.15 mm spacing. The USB D± pair was routed at 0.15 mm (default netclass width), which is slightly wider than the target — giving an estimated ~88 Ω, well within USB 2.0 Full Speed tolerance of 90 Ω ±15%. Note: stackup values updated from original PCBWay calculation (h = 0.1855 mm, Dk = 4.74, w = 0.2251 mm).
IPC-2141 impedance calculation — recalculated for JLCPCB stackup
Design constraints — JLCPCB manufacturing rules
Before routing, design rules were configured to match JLCPCB's JLC04161H-3313 stackup requirements: minimum trace width 0.15 mm (JLCPCB's manufacturing capability is 0.09 mm — a more conservative limit was set in KiCad), minimum via diameter 0.45 mm (drill 0.3 mm), hole-to-hole clearance 0.5 mm, copper-to-board-edge clearance 0.3 mm, and minimum annular ring 0.1 mm. Rules were applied as a KiCad DRC constraint file and a clean DRC pass was confirmed before routing began.
JLCPCB manufacturing constraints configured in KiCad design rules
Netclasses — power and signal net classification
Nets were grouped into custom netclasses before routing: PWR (VBUS, VCC, GND) assigned 0.3 mm minimum trace width to handle higher current paths; SIG (GPIO, SPI, I2C, UART) kept at default 0.15 mm. The USB differential pair (D+/D−) was routed at 0.15 mm width and 0.15 mm spacing using the default netclass — within USB 2.0 Full Speed tolerance.
Custom netclasses defined for power, signal, and USB differential pair
Phase 3 — Component Placement & 3D Verification
Strategic placement following signal flow and thermal considerations
Placed components following signal flow from USB-C through ESD protection, LDO, and ESP32-S3 module. Decoupling capacitors placed immediately adjacent to IC power pins.
3D model alignment and mechanical clearance review
Added STEP 3D models to all components. PTS810 buttons required X-rotation to 90°. Pin headers required Y-rotation 180° and Z-offset −1.5 mm for correct through-hole placement. Reviewed in KiCad 3D viewer before Gerber export.
Fig. 1 — Component Placement
Fig. 2 — 3D Model View
Phase 4 — Routing & Copper Pours
Impedance-controlled routing, differential pairs, and GND pours on all 4 layers
Routed USB D± using KiCad interactive differential pair router at 0.15 mm width, 0.15 mm spacing. Applied GND copper pours across all four layers with via stitching. Zone priorities set per-layer to resolve DRC intersection errors.
PCB editor — routed board with VISIBLE TOP LAYER TRACES
Key Engineering Decisions
Native USB over USB-to-UART bridge
Uses the ESP32-S3 built-in USB Serial/JTAG controller via
GPIO19 (D−) and GPIO20 (D+) instead of a CP2102N bridge. Eliminates one IC and reduces BOM cost without sacrificing programming or debug capability.USB D± impedance — IPC-2141 calculation for JLCPCB JLC04161H-3313
IPC-2141 edge-coupled microstrip calculation for the JLCPCB 3313 stackup (
h = 0.0994 mm, Dk = 4.4) gives a target width of 0.142 mm (5.59 mil) at 0.15 mm spacing for exactly 90 Ω. The pair was routed at 0.15 mm using the default netclass — slightly wider than the 0.142 mm target, giving an estimated impedance of ~88 Ω — well within the USB 2.0 Full Speed tolerance of 90 Ω ±15%.GPIO0, EN, and USB D± excluded from headers — replaced with power pins
GPIO0 is reserved for the BOOT button, EN for the RESET button, and GPIO19 (D−) / GPIO20 (D+) are routed directly to the USB-C connector — none of these are safe or useful to expose on a general-purpose header. The four positions freed up are replaced with additional power and ground pins: each header provides 3V3 and GND at the top (pins 1–2) and a second GND and 5V VBUS at the bottom (pins 21–22). This gives two ground references per header, which is practical for breadboard use and reduces the chance of floating grounds when connecting peripherals.4-layer stackup with dedicated GND plane on L2
Provides continuous GND reference directly beneath the signal layer, enabling impedance control for USB D±, reducing EMI from the ESP32-S3 Wi-Fi/BT radio, and providing a low-inductance return path for high-frequency signals.
LDO package selection based on thermal analysis
TLV75801 WSON-6 selected over SOT-23:
RθJA = 80.3°C/W vs 176.9°C/W. At 300mA load (P = 0.51W), WSON-6 gives only +41°C junction rise vs +90°C for SOT-23. Thermal pad soldered to GND copper pour.LDO feedback resistors — R3/R4 set Vout to 3.3V
R3 (1MΩ) and R4 (200kΩ) form the TLV75801 output voltage feedback divider. The 1:5 ratio sets the regulated output to 3.3V. Values chosen to minimise quiescent current through the divider while staying within the LDO's feedback input impedance spec.
Design Verification
0
DRC Errors
0
Unconnected Pads
0
Footprint Errors
(1 warning excluded)
(1 warning excluded)
Schematic Checks
USB-C CC resistors (5.1kΩ each)✓ Correct
EN pin pull-up (10kΩ to 3V3)✓ Present
GPIO0 boot pull-up✓ Internal (ESP32-S3)
I²C pull-ups on SDA/SCL✓ 10kΩ each
Decoupling caps — all ICs✓ 100nF + 10µF
BOOT strapping pin (GPIO0) excluded from header✓ GPIO0 protected
Layout Checks — JLCPCB Rules
USB DP routed — JLCPCB 3313 stackup✓ 0.15mm / 0.15mm
GND pours — all 4 layers✓ Distinct zone priorities
LDO thermal pad to GND✓ Confirmed
Hole to hole clearance ≥ 0.5mm✓ JLCPCB compliant
Copper to edge ≥ 0.3mm✓ JLCPCB compliant
3D model review✓ All placed & aligned
Future Improvements — Rev 2
LDO feedback divider — reduce resistor values in Rev 2
R3/R4 (1MΩ / 200kΩ) set Vout correctly but the high impedance increases sensitivity to PCB leakage. Rev 2 will scale down to
100kΩ / 20kΩ, maintaining the same output voltage while lowering source impedance and improving noise rejection.WS2812B power supply — Rev 2 fix required
Standard WS2812B minimum VDD is 3.5V; the current 3.3V supply is out of spec. Rev 2 will add 5V power to the LED and a level shifter on the DIN line so the logic high exceeds the 0.7×VDD input threshold. If using a 3.3V-compatible variant (e.g. WS2812B-V5), state the exact part number.
Footprint library consolidation
Migrate all custom footprints (ESP32-S3-MINI-1-N8, USB4105) into a project-local KiCad library to eliminate the footprint mismatch warnings in DRC and ensure reproducibility.
3V3 pin back-drive protection + bidirectional power input — Rev 2
Currently the
3V3 header pin is a regulated output only — do not apply external voltage to it. The TLV75801 LDO has no reverse current protection; powering through the 3V3 pin with USB disconnected back-drives the LDO output and can damage the IC. Rev 2 will add a series Schottky diode or ideal diode load switch on the LDO output, which will block reverse current and make it safe to power the board from an external 3.3V supply — enabling the board to run without USB-C.Consider ESP32-S3-MINI-1-N8R8 (PSRAM variant)
Same pinout and footprint as current module but adds 8MB PSRAM — no PCB changes required. Beneficial for display framebuffers, audio buffers, or any memory-intensive application.
